PCI configuration registers:
  Common header:
    0x00: 0x14631022 0x00000000 0x06000000 0x00800000

    Vendor Name: AMD (0x1022)
    Device Name: Family17h Data Fabric (0x1463)
    Command register: 0x0000
      I/O space accesses: off
      Memory space accesses: off
      Bus mastering: off
      Special cycles: off
      MWI transactions: off
      Palette snooping: off
      Parity error checking: off
      Address/data stepping: off
      System error (SERR): off
      Fast back-to-back transactions: off
      Interrupt disable: off
    Status register: 0x0000
      Immediate Readiness: off
      Interrupt status: inactive
      Capability List support: off
      66 MHz capable: off
      User Definable Features (UDF) support: off
      Fast back-to-back capable: off
      Data parity error detected: off
      DEVSEL timing: fast (0x0)
      Slave signaled Target Abort: off
      Master received Target Abort: off
      Master received Master Abort: off
      Asserted System Error (SERR): off
      Parity error detected: off
    Class Name: bridge (0x06)
    Subclass Name: host (0x00)
    Interface: 0x00
    Revision ID: 0x00
    BIST: 0x00
    Header Type: 0x00+multifunction (0x80)
    Latency Timer: 0x00
    Cache Line Size: 0bytes (0x00)

  Type 0 ("normal" device) header:
    0x10: 0x00000000 0x00000000 0x00000000 0x00000000
    0x20: 0x00000000 0x00000000 0x00000000 0x00000000
    0x30: 0x00000000 0x00000000 0x00000000 0x00000000

    Base address register at 0x10
      not implemented
    Base address register at 0x14
      not implemented
    Base address register at 0x18
      not implemented
    Base address register at 0x1c
      not implemented
    Base address register at 0x20
      not implemented
    Base address register at 0x24
      not implemented
    Cardbus CIS Pointer: 0x00000000
    Subsystem vendor ID: 0x0000
    Subsystem ID: 0x0000
    Expansion ROM Base Address Register: 0x00000000
      base: 0x00000000
      Expansion ROM Enable: off
      Validation Status: Validation not supported
      Validation Details: 0x0
    Reserved @ 0x34: 0x00000000
    Reserved @ 0x38: 0x00000000
    Maximum Latency: 0x00
    Minimum Grant: 0x00
    Interrupt pin: 0x00 (none)
    Interrupt line: 0x00

  Device-dependent header:
    0x40: 0x00000004 0x00000000 0x00000000 0x00000127
    0x50: 0x00000000 0x00000000 0x00000000 0x00000000
    0x60: 0x00000000 0x00000000 0x00000000 0x00000000
    0x70: 0x00000000 0x00000000 0x00000000 0x00000000
    0x80: 0x00000000 0x00000000 0x00000000 0x00000000
    0x90: 0x00000000 0x00000000 0x00000000 0x00000000
    0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xf0: 0x00000000 0x00000000 0x00000000 0x00000000